Detecting Delay Flaws by Very-Low-Voltage Testing

Delay test of chip I/Os using LSSD boundary scan

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Analysis of pattern-dependent and timing-dependent failures in an experimental test chip

ITC '98 Proceedings of the 1998 IEEE International Test Conference

Detecting resistive shorts for CMOS domino circuits

ITC '98 Proceedings of the 1998 IEEE International Test Conference

SHOrt voltage elevation (SHOVE) test for weak CMOS ICs

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium

6.3 Experimental Results for IDDQ and VLV Testing

VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium

Testing for Tunneling Opens

ITC '00 Proceedings of the 2000 IEEE International Test Conference

DELAY-FAULT TESTING AND DEFECTS IN DEEP SUB-MICRON ICS - DOES CRITICAL RESISTANCE REALLY MEAN ANYTHING?

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Getting Better Coverage from the Tests We Have

ITC '00 Proceedings of the 2000 IEEE International Test Conference

A BIST Approach for Very Deep Sub-Micron (VDSM) Defects

ITC '00 Proceedings of the 2000 IEEE International Test Conference

An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Testing for Resistive Opens and Stuck Opens

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Resistive Bridge Fault Modeling, Simulation and Test Generation

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Towards Reducing "Functional Only" Fails for the UltraSPARCTM Microprocessors

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs

IEEE Design & Test

Detection of Temperature Sensitive Defects Using ZTC

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip

Journal of Electronic Testing: Theory and Applications

Small-delay defect detection in the presence of process variations

Microelectronics Journal

Test set development for cache memory in modern microprocessors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

Journal of Electronic Testing: Theory and Applications

Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

System-level impact of chip-level failure mechanisms and screens

Proceedings of the International Conference on Computer-Aided Design