An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Detecting Delay Flaws by Very-Low-Voltage Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
Resistance Characterization for Weak Open Defects
IEEE Design & Test
Performance Comparison of VLV, ULV, and ECR Tests
Journal of Electronic Testing: Theory and Applications
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHY DEFECTS ESCAPE SOME OF OUR TESTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IDDT: fundamentals and test generation
Journal of Computer Science and Technology
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
IEEE Design & Test
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
A tunneling-open failure mode is proposed andcarefully studied. A circuit with a tunneling open couldpass at-speed Boolean tests but fail VLV testing or IDDQtesting. Theoretical calculations as well as Booleanand IDDQ experiments confirm the existence of tunnelingopens. The Murphy experimental data show that sevenout of nine VLV-only failure circuits can be explainedby this failure mode. All these seven circuits survived366 hours temperature burn-in. Finally, a cost effectivescreening strategy is proposed.