Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detecting resistive shorts for CMOS domino circuits
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SHOrt voltage elevation (SHOVE) test for weak CMOS ICs
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Bridges in sequential CMOS circuits: current-voltage signature
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Resistive Bridge Fault Modeling, Simulation and Test Generation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Test chip experimental results on high-level structural test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
How Many Test Vectors We Need to Detect a Bridging Fault?
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
System-level impact of chip-level failure mechanisms and screens
Proceedings of the International Conference on Computer-Aided Design
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Some weak static CMOS chips can be detected by testing them with a very low supply voltage-between 2 and 2.5 times the threshold voltage V/sub t/ of the transistors. A weak chip is one that contains a flaw-an imperfection that does not interfere with correct operation at rated conditions but which may cause intermittent or early-life failures. This paper considers several types of flaws and derives the test conditions for them. It also proposes two approaches for determining the appropriate test speed for very-low-voltage testing.