Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Pattern generation for a deterministic BIST scheme
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Seed encoding with LFSRs and cellular automata
Proceedings of the 40th annual Design Automation Conference
Efficient compression and application of deterministic patterns in a logic BIST architecture
Proceedings of the 40th annual Design Automation Conference
On Calculating Efficient LFSR Seeds for Built-In Self Test
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Efficient Seed Utilization for Reseeding based Compression
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BIST RESEEDING WITH VERY FEW SEEDS
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
BUILT-IN RESEEDING FOR SERIAL BIST
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
A SmartBIST Variant with Guaranteed Encoding
ATS '01 Proceedings of the 10th Asian Test Symposium
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Reseeding-Based Test Set Embedding with Reduced Test Sequences
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IEEE Design & Test
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimized reseeding by seed ordering and encoding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test embedding with discrete logarithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without explicitly loading a seed. The ATPG process is tuned to target only undetected faults as the PRPG goes through its natural sequence which is maximally used to generate useful test patterns. The test application procedure is slightly modified to enable higher flexibility and more reduction in tester storage and test time. The results of applying the technique show up to 90% reduction in tester storage and 80% reduction in test time compared to classic reseeding. They also show 70% improvement in defect coverage when the technique is emulated on test chips with real defects.