An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
OPMISR: the foundation for compressed ATPG vectors
Proceedings of the IEEE International Test Conference 2001
Multiple-output propagation transition fault test
Proceedings of the IEEE International Test Conference 2001
Quantitative analysis of very-low-voltage testing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Stuck-Fault Tests vs. Actual Defects
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Diagnosis of Sequence-Dependent Chips
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Test chip experimental results on high-level structural test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Visibility enhancement for silicon debug
Proceedings of the 43rd annual Design Automation Conference
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Journal of Electronic Testing: Theory and Applications
Sampling + DMR: practical and low-overhead permanent fault detection
Proceedings of the 38th annual international symposium on Computer architecture
Overcoming post-silicon validation challenges through quick error detection (QED)
Proceedings of the Conference on Design, Automation and Test in Europe
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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We at CRC have designed and LSI Logic has manufacturedtwo test chip designs;these were used to investigate thecharacteristics of actual production defects and theeffectiveness of various test techniques in detecting theirpresence. This paper presents a characterization of thedefects that shows that very few defective chips act as ifthey had a single-stuck fault present and that most of thedefects cause sequence-dependent behavior.A variety of techniques are used to reduce the size of testsets for digital chips. They typically rely on preserving thesingle-stuck-fault coverage of the test set. This strategydoesn't guarantee that the defect coverage is retained.This paper presents data obtained from applying a varietyof test sets on two chips (Murphy and ELF35) andrecording the test escapes. The reductions in test size canthus be compared with the increases in test escapes. Thedata shows that, even when the fault coverage is preserved,there is a penalty in test quality. Also presented is the datashowing the effect of reducing the fault coverage.Techniques studied include various single-stuck-faultmodels including inserting faults at the inputs of complexgates such as adders, multiplexers, etc. This technique iscompatible with the use of structural RTL netlists. Othertechniques presented include compaction techniques anddon't care bit assignment strategies.