Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Exploiting the on-chip inductance in high-speed clock distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ELF-Murphy Data on Defects and Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
SPEED CLUSTERING OF INTEGRATED CIRCUITS
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE Design & Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The act of applying a scan-based delay test to a chip can cause electrical disturbances in the power and clock distribution networks that affect the results of the test, either for better or for worse. Empirical data presented in this study suggest that altering the details of the delay test application protocol can have a significant effect on the test results, and thus the yield of the product being tested. Specifically, inserting wait states between scan shifting and the launch clock results in measurable yield improvement. Although the exact mechanisms involved remain elusive, the authors were able to eliminate several possibilities through a series of experiments. It is clear from these experiments that yield recovery is a real phenomenon, and that launch delay (LD) tests can help to recover from IR drop.