Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Proceedings of the 40th annual Design Automation Conference
Design and Analysis of Power Distribution Networks with Accurate RLC Models
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Inductance Aware Interconnect Scaling
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Power Distribution Networks in High Speed Integrated Circuits
Power Distribution Networks in High Speed Integrated Circuits
Inductance calculations in a complex integrated circuit environment
IBM Journal of Research and Development
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient early stage resonance estimation techniques for C4 package
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Handling inductance in early power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
IEEE Design & Test
Worst case power/ground noise estimation using an equivalent transition time for resonance
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special issue on ISCAS2008
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the International Conference on Computer-Aided Design
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.