Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Timing Analysis in Presence of Power Supply and Ground Voltage Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Effects of on-chip inductance on power distribution grid
Proceedings of the 2005 international symposium on Physical design
Power grid voltage integrity verification
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power Distribution Network Design for VLSI
Power Distribution Network Design for VLSI
An efficient dual algorithm for vectorless power grid verification under linear current constraints
Proceedings of the 47th Design Automation Conference
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Vectorless verification of RLC power grids with transient current constraints
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the International Conference on Computer-Aided Design
Constraint abstraction for vectorless power grid verification
Proceedings of the 50th Annual Design Automation Conference
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As part of integrated circuit design verification, one should check if the voltage drop on the power grid exceeds some critical threshold. One way to do this is by simulation, but that is computationally expensive and gets prohibitive for large circuits with a large variety of possible operational modes. Another limitation of a simulation-based approach is that it requires complete knowledge of the logic circuitry drawing current from the grid, thus precluding grid verification early in the design process. In this paper, we model the grid as an RLC circuit and we propose three verification techniques that can be applied in the early stages of the design process. These techniques do not require exact knowledge of the circuit currents. Instead, the currents drawn by the logic beneath the power grid are described by means of current constraints that capture the uncertainty about circuit details and activity. The first verification approach gives the exact worst-case voltage drop at every node of the grid, but it is slow. A second faster approach gives conservative bounds on the worst-case voltage drop at every node of the grid. The third approach is much faster; it is a conservative approach which simply checks if the grid voltage drop exceeds some pre-defined thresholds, without actually computing the worst-case voltage drop at every node.