Adaptive signal processing
Slope propagation in static timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case circuit delay taking into account power supply variations
Proceedings of the 41st annual Design Automation Conference
The care and feeding of your statistical static timer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient statistical timing analysis through error budgeting
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Handling inductance in early power grid verification
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Incremental and on-demand random walk for iterative power distribution network analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE - Transactions on Information and Systems
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and application of adaptive delay sequential elements
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Redundancy-aware electromigration checking for mesh power grids
Proceedings of the International Conference on Computer-Aided Design
A vectorless framework for power grid electromigration checking
Proceedings of the International Conference on Computer-Aided Design
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Given the sensitivity of circuit delay to supply and ground voltagevalues, static timing analysis (STA) must take into account supplyvoltage variations. Existing STA techniques allow one to verifythe timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independentnor totally dependent. In this work, we consider the supply andground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supplyvoltage values are not known exactly, but that only upper/lowerbounds on them are known. In this framework, we propose newtiming models for logic gates and identify the worst-case voltagecon gurations for individual gates and for simple paths. We thengive an STA technique that provides the worst-case circuit delaytaking supply variations into account.