Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Coping with buffer delay change due to power and ground noise
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing Analysis in Presence of Power Supply and Ground Voltage Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Improvement of power distribution network using correlation-based regression analysis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Proceedings of the 2008 international symposium on Physical design
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Gate delay estimation in STA under dynamic power supply noise
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with an equivalent power/ground voltage. This replacement reduces complexity that comes from the variety in noise waveform shape, and improves compatibility of power/ground noise aware timing analysis with conventional timing analysis framework. Experimental results show that the proposed approach can compute gate propagation delay considering temporal noise within 10% error in maximum and 0.5% in average.