Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Estimation of maximum current envelope for power bus analysis and design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A path selection algorithm for timing analysis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Dynamic Timing Analysis Considering Power Supply Noise Effects
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology trends in power-grid-induced noise
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Impact of Technology in Power-Grid-Induced Noise
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Analysis and Optimization of Power Grids
IEEE Design & Test
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Statistical Clock Skew Analysis Considering Intra-Die Process Variations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Timing analysis considering spatial power/ground level variation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Static timing analysis considering power supply variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Impact of Thermal Gradients on Clock Skew and Testing
IEEE Design & Test
Proceedings of the 2008 international symposium on Physical design
On-die CMOS voltage droop detection and dynamiccompensation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Timing Analysis Considering Spatial Power/Ground Level Variation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Timing Analysis Considering Temporal Supply Voltage Fluctuation
IEICE - Transactions on Information and Systems
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ICs
Microelectronics Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Clock buffer polarity assignment for power noise reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gate's worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.