Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Gate-level power and current simulation of CMOS integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
Noise aware behavioral modeling of the Ε-Δ fractional-N frequency synthesizer
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Effects of On-Chip Inductance on Power Distribution Grid
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Efficient Approach to Build Accurate Behavioral Models of PLL Designs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Modeling simultaneous switching noise-induced jitter for system-on-chip phase-locked loops
Proceedings of the 44th annual Design Automation Conference
Efficient modeling techniques for dynamic voltage drop analysis
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and design techniques for supply-noise mitigation in phase-locked loops
IEEE Transactions on Circuits and Systems Part I: Regular Papers
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Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy VDD waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some error may exist while compared with real simulation results. In this paper, a simple SCORE macromodel is proposed for PLL designs to help noiseaware behavioral models handle supply noise interaction effects. The time-varying supply noise waveform and real-time PLL responses can be obtained simultaneously with accurate noise estimations in this recursive approach. As demonstrated in the experimental results, the proposed approach can provide more realistic results with noise interaction effects but still keep fast simulation time.