Power estimation tool for sub-micron CMOS VLSI circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Compact vector generation for accurate power simulation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Gate-level power and current simulation of CMOS integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Effects of on-chip inductance on power distribution grid
Proceedings of the 2005 international symposium on Physical design
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Accurate current estimation for interconnect reliability analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Since the IC technology scales down the effect of voltage drop/ground bounce becomes increasingly significant. Voltage drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can cause IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. in this paper, we propose efficient modeling techniques for analyzing power distribution in deep sub micron (DSM) ASIC designs. Current Source-based Model (CSM) and Voltage Controlled Resistor (VCR) are the key concepts in our approach. A basic prerequisite for the new approach are CMOS standard libraries that are pre-characterized with respect to the corresponding modeling requirements. This paper also presents an approach for this characterization step. The proposed techniques can efficiently handle multiple-input-switching (MIS), including single-input-switching events (SIS) and provide good analysis results compared to the reference with two orders of magnitude speedup, although the cell library pre-characterization is based on SPICE simulations. Our model is independent of the power network context, which implies that different power distribution networks may be analyzed based on the same model and the same cell characterizations. The run-time, memory and accuracy efficiency of the proposed method are demonstrated on an industrial design.