An electromagnetic approach for modeling high performance computer packages
IBM Journal of Research and Development
Optimization techniques for high-performance digital circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Estimation of maximum power supply noise for deep sub-micron designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
EMI-noise analysis under ASIC design environment
ISPD '99 Proceedings of the 1999 international symposium on Physical design
A floorplan-based planning methodology for power and clock distribution in ASICs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Converting a 64b PowerPC processor from CMOS bulk to SOI technology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Layout tools for analog ICs and mixed-signal SoCs: a survey
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Power supply design parameters prediction for high performance IC design flows
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
On the interaction of power distribution network with substrate
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Macro-modeling concepts for the chip electrical interface
Proceedings of the 39th annual Design Automation Conference
Modeling and analysis of regular symmetrically structured power/ground distribution networks
Proceedings of the 39th annual Design Automation Conference
Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits
Analog Integrated Circuits and Signal Processing
Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows
Analog Integrated Circuits and Signal Processing
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation and optimization of the power distribution network in VLSI circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Analysis and Optimization of Power Grids
IEEE Design & Test
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Noise Safety Design Methodologies
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Dynamic Timing Analysis Considering Power Supply Noise Effects
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Energy-reliability trade-off for NoCs
Networks on chip
Delay Testing Considering Power Supply Noise Effects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Analysis of blocking dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
Clock network sizing via sequential linear programming with time-domain analysis
Proceedings of the 2004 international symposium on Physical design
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DEPOGIT: dense power-ground interconnect architecture for physical design integrity
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
EM Wave Coupling Noise Modeling Based on Chebyshev Approximation and Exact Moment Formulation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Performance Driven Decoupling Capacitor Allocation Considering Data and Clock Interactions
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power Grid Planning for Microprocessors and SOCS
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI
Analog Integrated Circuits and Signal Processing
Effects of on-chip inductance on power distribution grid
Proceedings of the 2005 international symposium on Physical design
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Partitioning-based approach to fast on-chip decap budgeting and minimization
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Multi-story power delivery for supply noise reduction and low voltage operation
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Floorplanning with power supply noise avoidance
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming
Proceedings of the 43rd annual Design Automation Conference
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Fast decap allocation based on algebraic multigrid
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
Integration, the VLSI Journal
A new twisted differential line structure in global bus design
Proceedings of the 44th annual Design Automation Conference
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Efficient modeling techniques for dynamic voltage drop analysis
Proceedings of the 44th annual Design Automation Conference
Power Grid Physics and Implications for CAD
IEEE Design & Test
Polymer self assembly in semiconductor microelectronics
IBM Journal of Research and Development
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks
Integration, the VLSI Journal
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Clock-tree synthesis for low-EMI design
Journal of Embedded Computing - PATMOS 2007 selected papers on low power electronics
Locality-driven parallel power grid optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and accurate analysis of supply noise effects in PLL with noise interactions
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Passive and active reduction techniques for on-chip high-frequency digital power supply noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-die power grids: the missing link
Proceedings of the 47th Design Automation Conference
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
An efficient decoupling capacitance optimization using piecewise polynomial models
Proceedings of the Conference on Design, Automation and Test in Europe
EMC-aware design on a microcontroller for automotive applications
Proceedings of the Conference on Design, Automation and Test in Europe
Locality-Driven Parallel Static Analysis for Power Delivery Networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Power supply selective mapping for accurate timing analysis
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Efficient simulation of power/ground networks with package and vias
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Spectral analysis of the on-chip waveforms to generate guidelines for EMC-aware design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Minimizing power supply noise through harmonic mappings in networks-on-chip
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Clock distribution techniques for Low-EMI design
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
A study of tapered 3-D TSVs for power and thermal integrity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors.Based on an integrated package-level andchip-level power bus model, and a simulated switching circuitmodel for each functional block, this methodology offersthe most complete and accurate analysis of Vdd distributionfor the entire chip. The analysis results not only providedesigners with the inductive 驴I noise and the resistive IRdrop data at the same time, but also allow designers to easilyidentify the hot spots on the chip and 驴V across the chip.Global and local optimization such as buffer sizing, powerbus sizing, and on-chip decoupling capacitor placement canthen be conducted to maximize the circuit performance andminimize the noise.