Introduction to algorithms
Operations research: deterministic optimization models
Operations research: deterministic optimization models
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Full-chip verification methods for DSM power distribution systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods
Proceedings of the 38th annual Design Automation Conference
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Proceedings of the 2002 international symposium on Physical design
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Modeling and analysis of regular symmetrically structured power/ground distribution networks
Proceedings of the 39th annual Design Automation Conference
VeriCDF: a new verification methodology for charged device failures
Proceedings of the 39th annual Design Automation Conference
Design and Analysis of Power Integrity in Deep Submicron System-on-Chip Circuits
Analog Integrated Circuits and Signal Processing
Frequency domain analysis of switching noise on power supply network
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multigrid-like technique for power grid analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Impact of Low-Impedance Substrate on Power Supply Integrity
IEEE Design & Test
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
Supply Voltage Degradation Aware Analytical Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A hierarchical analysis methodology for chip-level power delivery with realizable model reduction
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analysis of buffered hybrid structured clock networks
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient decoupling capacitor planning via convex programming methods
Proceedings of the 2006 international symposium on Physical design
An Improved AMG-based Method for Fast Power Grid Analysis
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Stochastic variational analysis of large power grids considering intra-die correlations
Proceedings of the 43rd annual Design Automation Conference
Analysis of Power Supply Noise in the Presence of Process Variations
IEEE Design & Test
ETBR: extended truncated balanced realization method for on-chip power grid network analysis
Proceedings of the conference on Design, automation and test in Europe
The road to 3D EDA tool readiness
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Stochastic power/ground supply voltage prediction and optimization via analytical placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Decoupling capacitance efficient placement for reducing transient power supply noise
Proceedings of the 2009 International Conference on Computer-Aided Design
Incremental solution of power grids using random walks
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Efficient power grid integrity analysis using on-the-fly error check and reduction
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
PowerRush: a linear simulator for power grid
Proceedings of the International Conference on Computer-Aided Design
Fast Poisson solver preconditioned method for robust power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Optimization of on-chip switched-capacitor DC-DC converters for high-performance applications
Proceedings of the International Conference on Computer-Aided Design
PowerRush: efficient transient simulation for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Placement optimization of power supply pads based on locality
Proceedings of the Conference on Design, Automation and Test in Europe
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Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated through the analysis of case studies of several multi-million node power grids, extracted from real microprocessor and DSP designs.