Decoupling capacitance allocation for power supply noise suppression

Authors:
Shiyou Zhao;Kaushik Roy;Cheng-Kok Koh
Affiliations:
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
Proceedings of the 2001 international symposium on Physical design
Year:
2001

Citing 9
Cited 23

Automatic sizing of power/ground (P/G) networks in VLSI

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design

DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-pad power/ground network design for uniform distribution of ground bounce

DAC '98 Proceedings of the 35th annual Design Automation Conference
Incremental physical design

ISPD '00 Proceedings of the 2000 international symposium on Physical design
Hierarchical analysis of power distribution networks

Proceedings of the 37th Annual Design Automation Conference
Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources

Proceedings of the 37th Annual Design Automation Conference
Fast analysis and optimization of power/ground networks

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simulation and optimization of the power distribution network in VLSI circuits

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-Micron CMOS Circuits

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Proceedings of the 2002 international symposium on Physical design
Analysis and Optimization of Power Grids

IEEE Design & Test
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
DEPOGIT: dense power-ground interconnect architecture for physical design integrity

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Two-Level Power-Grid Model for Transient Current Testing Evaluation

Journal of Electronic Testing: Theory and Applications
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation

Proceedings of the 42nd annual Design Automation Conference
Supply Voltage Degradation Aware Analytical Placement

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Floorplanning with power supply noise avoidance

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
VLSI on-chip power/ground network optimization considering decap leakage currents

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Efficient decoupling capacitor planning via convex programming methods

Proceedings of the 2006 international symposium on Physical design
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming

Proceedings of the 43rd annual Design Automation Conference
Vertical via design techniques for multi-layered P/G networks

Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Minimum decoupling capacitor insertion in VLSI power/ground supply networks by semidefinite and linear programs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A Relocation Method for Circuit Modifications

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Stochastic power/ground supply voltage prediction and optimization via analytical placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal design of the power-delivery network for multiple voltage-island system-on-chips

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of via distribution and stacked via in multi-layered P/G networks

Integration, the VLSI Journal
Passive and active reduction techniques for on-chip high-frequency digital power supply noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock buffer polarity assignment for power noise reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Supply noise suppression by triple-well structure

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on the power supply noise estimates. A linear programming technique is used to maximize the allocation of the existing white space in the floorplan for the placement of decoupling capacitors. An incremental heuristic is proposed to insert more white space into the existing floorplan to meet the remaining demand required for decoupling capacitance fabrication. Experimental results on six MCNC benchmark circuits show that the white space allocated for decoupling capacitance is about 6%-12% of the chip area for the 0.25&mgr;&mgr; technology, and the power supply noise can be kept below 10%Vdd.