Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Post-placement residual-overlap removal with minimal movement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Decoupling capacitance allocation for power supply noise suppression
Proceedings of the 2001 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
On legalization of row-based placements
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A congestion-driven placement framework with local congestion prediction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Diffusion-based placement migration
Proceedings of the 42nd annual Design Automation Conference
Computational geometry based placement migration
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we propose a novel migration method. In this method, the resultant placement retains the structure of the original placement, called model placement, as much as possible. For this purpose, we minimize the sum of the difference in area between the model placement and the relocated one and the total amount of displacement between them. Moreover, to achieve a short runtime, we limit the solution space and change the packing origin in the optimization process. We construct the system on Sequence-Pair. Experimental results show that our approach preserves the chip area and the overall circuit structure with 98% less runtime than that realized by naive simulated annealing.