Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Routability-driven repeater block planning for interconnect-centric floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Noise-aware buffer planning for interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A Watermarking System for IP Protection by Buffer Insertion Technique
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An integrated nonlinear placement framework with congestion and porosity aware buffer planning
Proceedings of the 45th annual Design Automation Conference
A Relocation Method for Circuit Modifications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Improved performance and yield with chip master planning design methodology
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Integration, the VLSI Journal
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information theoretic modeling and analysis for global interconnects with process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper studies buffer block planning (BBP) for interconnect planning and prediction in deep submicron designs. We first introduce the concept of feasible region for buffer insertion, and derive its closed-form formula. We observe that the feasible region for a buffer is quite large in general even under fairly tight delay constraint. Therefore, it gives us a lot of flexibility to plan for buffer locations. We then develop an effective BBP algorithm to perform buffr clustering such that design objectives such as overall chip area and the number of buffer blocks can be minimized. Effective BBP can plan and predict system-level interconnect by construction, so that accurate interconnect information can be used in early design stages to ensure design closure.