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In this paper a shift is proposed in the design of vlsi circuits. In conventional design higher levels of synthesis have to deliver a gate and net list, from which layout synthesis has to built a mask specification for manufacturing. Analysis, mainly timing analysis, is built in a feedback loop to catch violations of timing requirements before sign-off. These violations are used to hand an updated specification to synthesis. Such iteration is not desirable, and for really high performance not feasible. To come to a design flow, higher level synthesis should distribute delay over the functional elements and interconnect, and layout synthesis should use its degrees of freedom to realize those delays.