Accurate estimation of global buffer delay within a floorplan

Authors:
C. J. Alpert;Jiang Hu;S. S. Sapatnekar;C. N. Sze
Affiliations:
IBM Corp., Austin, TX, USA;Dept. of Electr. & Comput. Eng., Minnesota Univ., Twin Cities, MN, USA;Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada;Dept. of Inf. & Comput. Sci., Linkoping Univ., Sweden
Venue:
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Year:
2004

Citing 12
Cited 9

Performance optimization of VLSI interconnect layout

Integration, the VLSI Journal
Wire segmenting for improved buffer insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Proceedings of the 1997 international symposium on Physical design
Global wires: harmful?

ISPD '98 Proceedings of the 1998 international symposium on Physical design
Routing tree construction under fixed buffer locations

Proceedings of the 37th Annual Design Automation Conference
Buffer block planning for interconnect-driven floorplanning

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer insertion with adaptive blockage avoidance

Proceedings of the 2002 international symposium on Physical design
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages

Proceedings of the 2002 international symposium on Physical design
A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The scaling challenge: can correct-by-construction design help?

Proceedings of the 2003 international symposium on Physical design
Fast and flexible buffer trees that navigate the physical layout environment

Proceedings of the 41st annual Design Automation Conference
Interconnect performance estimation models for design planning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Path based buffer insertion

Proceedings of the 42nd annual Design Automation Conference
The scaling of interconnect buffer needs

Proceedings of the 2006 international workshop on System-level interconnect prediction
Efficient algorithms for buffer insertion in general circuits based on network flow

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Improving voltage assignment by outlier detection and incremental placement

Proceedings of the 44th annual Design Automation Conference
Techniques for effective distributed physical synthesis

Proceedings of the 44th annual Design Automation Conference
ECO timing optimization using spare cells

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Circuit-wise buffer insertion and gate sizing algorithm with scalability

Proceedings of the 45th annual Design Automation Conference
Incremental improvement of voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ECO timing optimization using spare cells and technology remapping

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer insertion solution unrealizable. The theory of Otten (1998) is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution. Potential applications include wire planning, timing analysis during floorplanning or global routing. Our experiments show that our approach accurately predicts delay when compared to constructing a realizable buffer insertion with multiple buffer types.