Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
An algebraic multigrid solver for analytical placement with layout based clustering
Proceedings of the 40th annual Design Automation Conference
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
APlace: a general analytic placement framework
Proceedings of the 2005 international symposium on Physical design
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast and robust quadratic placement combined with an exact linear net model
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design hierarchy-guided multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
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We present two techniques, (1) placement-based timing-driven partitioner (PTP) and (2) virtual physical synthesis based budgeter (VSB), that support effective distributed physical synthesis.