Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Improving Placement under the Constant Delay Model
Proceedings of the conference on Design, automation and test in Europe
Fast Comparisons of Circuit Implementations
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Techniques for effective distributed physical synthesis
Proceedings of the 44th annual Design Automation Conference
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Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations--the minimum achievable delay and the cost of achieving a target delay--and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.