Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Improving Placement under the Constant Delay Model
Proceedings of the conference on Design, automation and test in Europe
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact transistor sizing based on iterative relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-Form bounds for interconnect-aware minimum-delay gate sizing
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing can drastically improve circuit performance, by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the attainable circuit delay can be determined only after running the tool. In this paper, we present an approach for fast transistor sizing that can enable a designer to choose one among several functionally identical implementations. Our algorithm computes the minimum achievable delay of a circuitwith a maximum average error of 5.5% in less than a second for even the largest benchmarks.