Evaluation of function blocks for asynchronous design
EURO-DAC '94 Proceedings of the conference on European design automation
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
ISPD '98 Proceedings of the 1998 international symposium on Physical design
DAC '98 Proceedings of the 35th annual Design Automation Conference
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Area and search space control for technology mapping
Proceedings of the 37th Annual Design Automation Conference
Optimal P/N width ratio selection for standard cell libraries
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Locally clocked pipelines and dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic Synthesis and Verification
Technology-based transformations
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simultaneous gate sizing and fanout optimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An exact gate assignment algorithm for tree circuits under rise and fall delays
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The Counterflow Pipeline Processor Architecture
IEEE Design & Test
A Delay Model for Router Microarchitectures
IEEE Micro
Synthesis and placement flow for gain-based programmable regular fabrics
Proceedings of the 2003 international symposium on Physical design
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Physical synthesis methodology for high performance microprocessors
Proceedings of the 40th annual Design Automation Conference
Buffered Routing Tree Construction Under Buffer Placement Blockages
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Fast Comparisons of Circuit Implementations
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Proceedings of the 43rd annual Design Automation Conference
Timing optimization in logic with interconnect
Proceedings of the 2008 international workshop on System level interconnect prediction
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic synthesis for reducing leakage power consumption under workload uncertainty
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Physical realization oriented area-power-delay tradeoff exploration
SOC'09 Proceedings of the 11th international conference on System-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit design style for energy efficiency: LSDL and compound domino
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Methodology for energy-efficient digital circuit sizing: important issues and design limitations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Soft error-aware power optimization using gate sizing
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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