The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Performance-oriented technology mapping
Performance-oriented technology mapping
New algorithms for gate sizing: a comparative study
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A simple algorithm for fanout optimization using high-performance buffer libraries
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Interleaving buffer insertion and transistor sizing into a single optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Simultaneous gate sizing and placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum-buffered routing of non-critical nets for slew rate and reliability control
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Low-power fanout optimization using multi threshold voltages and multi channel lengths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a non-convex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a non-linear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 9.2% compared to conventional flows that separate gate sizing from fanout optimization.