The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
A heuristic algorithm for the fanout problem
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
BooleDozer: logic synthesis for ASICs
IBM Journal of Research and Development
A simple algorithm for fanout optimization using high-performance buffer libraries
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Minimization of chip size and power consumption of high-speed VLSI buffers
Proceedings of the 1997 international symposium on Physical design
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Simultaneous gate sizing and fanout optimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Simultaneous Vt selection and assignment for leakage optimization
Proceedings of the 2003 international symposium on Low power electronics and design
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Convex Optimization
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Low-power fanout optimization using multiple threshold voltage inverters
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-power fanout optimization using MTCMOS and multi-Vt techniques
Proceedings of the 2006 international symposium on Low power electronics and design
A fanout optimization algorithm based on the effort delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the problem of low-power fanout optimization for near-continuous-size inverter libraries. It is demonstrated that because of neglecting short-circuit current, previous techniques proposed to optimize the area of a fanout tree may result in excessive power consumption. This paper describes how the problem of low-power fanout optimization can be reduced to inverter-chain optimization problem and formulates the minimization of the total power consumption of an inverter chain as a geometric program. Moreover, it describes an efficient method to minimize the total power consumption of a fanout tree by using multiple-channel-length (multi-LGate) and multiple-threshold-voltage (multi-Vt) techniques. Experimental results show that the proposed technique can reduce the power consumption of the fanout trees by an average of 11.17% over SIS fanout-optimization program.