Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Future performance challenges in nanometer design
Proceedings of the 38th annual Design Automation Conference
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
CMOS design near the limit of scaling
IBM Journal of Research and Development
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exploring the limits of leakage power reduction in caches
ACM Transactions on Architecture and Code Optimization (TACO)
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Area optimization for leakage reduction and thermal stability in nanometer scale technologies
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An analytical state dependent leakage power model for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Digital Circuit Optimization via Geometric Programming
Operations Research
Proceedings of the 44th annual Design Automation Conference
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
On Composite Leakage Current Maximization
Journal of Electronic Testing: Theory and Applications
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Low-power fanout optimization using multi threshold voltages and multi channel lengths
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Full-chip leakage analysis for 65nm CMOS technology and beyond
Integration, the VLSI Journal
Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure
Journal of Computational Electronics
An optimization mechanism intended for static power reduction using dual-Vth technique
Journal of Electrical and Computer Engineering
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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In this paper we address the growing issue of gate oxide leakage current (Igate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both Igate and subthreshold leakage (Isub). The interaction between Isub and Igate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of Igate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce Igate. We find that for technologies with appreciable Igate, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for Isub reduction.