Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors
Proceedings of the 2002 international symposium on Low power electronics and design
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime
Proceedings of the 2003 international symposium on Low power electronics and design
Simultaneous Vt selection and assignment for leakage optimization
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage in nano-scale technologies: mechanisms, impact and design considerations
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Row/column redundancy to reduce SRAM leakage in presence of random within-die delay variation
Proceedings of the 13th international symposium on Low power electronics and design
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and analysis of two low-power SRAM cell structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Circuit-level design approaches for radiation-hard digital electronics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM
Integration, the VLSI Journal
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in very deep submicron regime. As a result, reducing the subthreshold and gate-tunneling leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual-Vt and dual-Tox assignment to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that the read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different types of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. Simulation results with a 65nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64Kb SRAM by more than 50%.