Tradeoffs between date oxide leakage and delay for dual Tox circuits

Authors:
Anup Kumar Sultania;Dennis Sylvester;Sachin S. Sapatnekar
Affiliations:
University of Minnesota, Minneapolis, MN;University of Michigan, Ann Arbor, MI;University of Minnesota, Minneapolis, MN
Venue:
Proceedings of the 41st annual Design Automation Conference
Year:
2004

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Abstract

Gate oxide tunneling current (Igate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (Tox) goes below 15AA. Increasing the value of Tox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible Tox values to each transistor. In this paper, we propose an algorithm for dual Tox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low Tox, our approach achieves an average leakage reduction of 83% under 100nm models.