Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
IEEE Design & Test
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
| Hi-index | 0.00 |
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorithm for the gate leakage current reduction by simultaneous scheduling, allocation and binding during behavioral synthesis. Gate leakage current reduction is based on the use of functional units of different oxide thickness while simultaneously accounting for process variations. We present a cost function that minimizes leakage and area overhead. The algorithm minimizes the cost function for a given delay trade-off factor. It uses a pre-characterized cell library for tunneling current, delay and area, expressed as analytical functions of the gate oxide thickness Tox. We tested our approach using a number of behavioral level benchmark circuits characterized for a 45nm library by integrating our algorithm into a high-level synthesis system. We obtained an average gate leakage reduction of 76.88% with an average area overhead of 17.38% for different delay trade-off factors ranging from 1.0 to 1.4.