Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
A framework for energy and transient power reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO
Microelectronics Journal
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As a result of aggressive technology scaling, gate leakage (gate oxide direct tunneling) has become a major component of total power dissipation. Use of dielectrics of higher permittivity (Dual-K) or use of silicon dioxide of higher thicknesses (Dual-T ) are being considered as methods for its reduction. This paper presents a comparative view of dual dielectric and dual thickness low leakage design techniques from a behavioral synthesis perspective. An algorithm is presented for the gate leakage current reduction that does simultaneous scheduling, allocation and binding during behavioral synthesis while accounting for process variations. The algorithm minimizes the gate leakage for given time constraints. We performed experiments for a number of benchmark circuits using a 45nm CMOS technology datapath library. We obtained gate leakage reduction as high as 95% for the dual-K (SiO_2 and Si3N_4) and 91% for the dual-T (1.4nm and 1.7nm) approaches. It is observed that the dual-K approach outperformed the dual-T approach for all benchmark circuits.