An implicit connection graph maze routing algorithm for ECO routing
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Performance optimization under rise and fall parameters
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
On the global fanout optimization problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
Legalizing a placement with minimum total movement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO
Microelectronics Journal
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
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Abstract-With continued and aggressive scaling, using ultralow thickness SiO2 for the transistor gates, tunneling current has emerged as the major component of leakage in CMOS circuits. In this paper, we propose a new approach called dual dielectrics of dual thicknesses (DKDT) for the reduction of both ON and OFF state gate tunneling currents. We claim that the simultaneous utilization of SiON and SiO2 each with multiple thicknesses is a better approach for gate leakage reduction than the conventional one that uses a single gate dielectric, SiO2, of multiple thicknesses. We develop an algorithm for the corresponding assignment of dual dielectric and dual thickness cells that minimizes the overall tunneling current for a circuit without compromising its performance. We performed extensive experiments on ISCAS驴85 benchmarks using 45 nm technology which demonstrate that our approach can reduce the tunneling current by as much as 98.7% on average 94.8%), without performance degradation.