Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs)
ATS '98 Proceedings of the 7th Asian Test Symposium
A comparative study of MOS VCOs for low voltage high performance operation
Proceedings of the 2004 international symposium on Low power electronics and design
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Dual-K Versus Dual-T Technique for Gate Leakage Reduction: A Comparative Perspective
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design and Analysis of Experiments
Design and Analysis of Experiments
CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
ULS: A dual-Vth/high-κ nano-CMOS universal level shifter for system-level power management
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Proceedings of the 20th symposium on Great lakes symposium on VLSI
New design of 3.2---4.8 GHz generator for multi-bands architecture of UWB communication
Analog Integrated Circuits and Signal Processing
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Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an ''effective tunneling capacitance'', which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.