Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

Authors:
Georges Gielen;Wim Dehaene;Phillip Christie;Dieter Draxelmayr;Edmond Janssens;Karen Maex;Ted Vucurevich
Affiliations:
K.U. Leuven, Belgium;K.U. Leuven, Belgium;Philips, The Netherlands;Infineon, Austria;ST Microelectronics, Belgium;IMEC, Belgium;Cadence, USA
Venue:
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2005

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Abstract

This special session adresses the problems that designers face when implementing analogand digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel ofexperts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.