Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
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Although industry-wide adoption of 65nm technology is in its infancy, major foundries have started developing design kits for the 65nm base. For designers, this means managing new and complex process variability and interconnect issues, relevant to specific design flows, using advanced parasitic extraction methodologies.