Systematic simulation-based predictive synthesis of integrated optical interconnect

Authors:
Ian O'Connor;Faress Tissafi-Drissi;Frédéric Gaffiot;Joni Dambre;Michiel De Wilde;Joris Van Campenhout;Dries Van Thourhout;Jan Van Campenhout;Dirk Stroobandt
Affiliations:
Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, France;Mixed-Signal Design Department, Dolphin Integration, Meylan, France and Lyon Institute of Technology, Ecole Centrale de Lyon, Ecully, France;Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, Ecully, France;Electronics and Information Systems Department, Ghent University, Ghent, Belgium;Electronics and Information Systems Department, Ghent University, Ghent, Belgium;Electronics and Information Systems Department, Ghent University, Ghent, Belgium;INTEC Department, Ghent University, Ghent, Belgium;Electronics and Information Systems Department, Ghent University, Ghent, Belgium;Electronics and Information Systems Department, Ghent University, Ghent, Belgium
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

Citing 2
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Abstract

Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthesis method for integrated microsource-based optical interconnect capable of optimally sizing the interface circuits based on system specifications, CMOS technology data, and optical device characteristics. The simulation-based nature of the design method means that its results are relatively accurate, even though the generation of each data point requires only 5 min on a 1.3-GHz processor. This method has been used to extract typical performance metrics (delay, power, interconnect density) for optical interconnect of length 2.5-20 mm in three predictive technologies at 65-, 45-, and 32-nm gate length.