A Reconfigurable Platform for the Automatic Synthesis of Analog Circuits
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Emerging yield and reliability challenges in nanometer CMOS technologies
Proceedings of the conference on Design, automation and test in Europe
Automated critical device identification for configurable analogue transistors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) structure is presented that allows the adjustment of devices after manufacture. The technique enables both performance and yield to be improved as part of the normal test process. The optimal sizing of the inserted CAT devices is crucial to ensure the greatest improvement in yield and this paper considers this challenge in detail. An analysis and description of the underlying theory of the sizing problem is given along with examples of incorrect sizing. Guidelines to achieve optimal CAT sizing are proposed, and results are provided to demonstrate the overall effectiveness of the CAT approach.