Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Emerging yield and reliability challenges in nanometer CMOS technologies
Proceedings of the conference on Design, automation and test in Europe
Optimal sizing of configurable devices to reduce variability in integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
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A novel approach is proposed for analogue circuits that identifies which devices should be replaced with configurable analogue transistors (CATs) to maximise post fabrication yield. Both performance sensitivity and adjustment independence are considered when identifying these critical devices, giving a combined weighted sensitivity. The results from an operational amplifier case study are presented where it is demonstrated that variation in key circuit performances can be reduced by an average of 78.8% with the use of only three CATs. These results confirm that the proposed critical device selection method with optimal performance driven CAT sizing can lead to significant improvement in overall performance and yield.