Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Latin hypercube sampling of Gaussian random fields
Technometrics
Proceedings of the 38th annual Design Automation Conference
Dynamic Programming and Optimal Control
Dynamic Programming and Optimal Control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Application-specific worst case corners using response surfaces and statistical models
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic Probability Extraction for Nonnormal Performance Distributions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case analysis and optimization of VLSI circuit performances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Proceedings of the International Conference on Computer-Aided Design
Automated critical device identification for configurable analogue transistors
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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The well-known Pelgrom model [14] has demonstrated that the variation between two devices on the same die due to random mismatch is inversely proportional to the square root of the device area: σ ~ 1/sqrt(Area). Based on the Pelgrom model, analog devices are sized to be large enough to average out random variations. Importantly, with CMOS scaling, variations due to random doping fluctuations are making it exceedingly difficult to control device mismatches by sizing alone; namely, the devices have to be made so large that the benefits of CMOS scaling are not realized for analog and RF circuits. In this paper we propose a novel post-silicon tuning methodology to reduce random mismatches for analog circuits in sub-90nm CMOS. A novel dynamic programming algorithm is incorporated into a fast Monte Carlo simulation flow for statistical analysis and optimization of the proposed tunable analog circuits. We apply the proposed post-silicon tuning methodology to several commonly-used analog circuit blocks. We demonstrate that with the post-silicon tuning, device mismatch exponentially decreases as area increases: σ ~ exp(---α·Area).