Structured analog circuit design and MOS transistor decomposition for high accuracy applications

Authors:
Bo Yang;Qing Dong;Jing Li;Shigetoshi Nakatake
Affiliations:
The University of Kitakyushu, Hibikino, Wakamatsu, Kitakyushu, Japan;The University of Kitakyushu, Hibikino, Wakamatsu, Kitakyushu, Japan;The University of Kitakyushu, Hibikino, Wakamatsu, Kitakyushu, Japan;The University of Kitakyushu, Hibikino, Wakamatsu, Kitakyushu, Japan
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2010

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Abstract

This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog design based on the transistor array are applicable. Also our test chip shows that design with transistor array can suppress the variation of Vth stemmed from CMP process. Based on this conclusion, we propose a simple framework with transistor array for structured analog layout generation, which involves the transistor decomposition. Using this framework, we generate several layouts for a typical CMOS OPAMP circuit and compare the automatically generated layouts with the manual layouts. Although the layout sizes of the transistor array based OPAMPs are slightly bigger than that of the manual designs, the automatic layout generation is much faster than manually synthesizing the layout.