DFT/FFT and Convolution Algorithms: Theory and Implementation
DFT/FFT and Convolution Algorithms: Theory and Implementation
Filling algorithms and analyses for layout density control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2001 international symposium on Physical design
Hierarchical dummy fill for process uniformity
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Closing the smoothness and uniformity gap in area fill synthesis
Proceedings of the 2002 international symposium on Physical design
Area Fill Generation With Inherent Data Volume Reduction
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Dummy fill density analysis with coupling constraints
Proceedings of the 2007 international symposium on Physical design
Is your layout density verification exact?: a fast exact algorithm for density calculation
Proceedings of the 2007 international symposium on Physical design
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Full-chip routing system for reducing Cu CMP & ECP variation
Proceedings of the 21st annual symposium on Integrated circuits and system design
Provably good and practically efficient algorithms for CMP dummy fill
Proceedings of the 46th Annual Design Automation Conference
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Proceedings of the International Conference on Computer-Aided Design
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
Proceedings of the 2013 ACM international symposium on International symposium on physical design
An efficient method for gradient-aware dummy fill synthesis
Integration, the VLSI Journal
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Chemical-mechanical polishing (CMP) is an enabling technique used in deep-submicron VLSI manufacturing to achieve uniformity in long range oxide planarization [1]. Post-CMP oxide topography is highly related to local spatial pattern density in layout. To change local pattern density, and thus ensure post-CMP planarization, dummy features are placed in layout. Based on models that accurately describe the relation between local pattern density and post-CMP planarization [7; 5; 9], a two-step procedure of global density assignment followed by local insertion is proposed to solve the dummy feature placement problem in the fixed-dissection regime with both single-layer and multiple-layer considerations. Two experiments, conducted with real design data, gave excellent results by reducing post-CMP topography variation from 767Å to 152Å in the single-layer formulation and by avoiding cumulative effect in the multiple-layer formulation. The result from single-layer formulation compares very favorably both to the rule-based approach widely used in industry and to the algorithm in [3]. The multiple-layer formulation has no previously published work.