Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
Practical iterated fill synthesis for CMP uniformity
Proceedings of the 37th Annual Design Automation Conference
Monte-Carlo algorithms for layout density control
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 international symposium on Physical design
Hierarchical dummy fill for process uniformity
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Adoption of OPC and the impact on design and layout
Proceedings of the 38th annual Design Automation Conference
Filling algorithms and analyses for layout density control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Is your layout density verification exact?: a fast exact algorithm for density calculation
Proceedings of the 2007 international symposium on Physical design
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Control of variability and performance in the back end of the VLSI manufacturing line has become extremely difficult with the introduction of new materials such as copper and low-k dielectrics. Uniformity of chemical-mechanical planarization (CMP) requires the insertion of area fill features into the layout, in order to smoothen the variation of feature densities across the die and thus improve manufacturability. Because the size of area fill features is very small compared with the large empty layout areas that must be filled, the filling process can increase the size of a GDSII file by an order of magnitude or more. Data compression is therefore a significant issue in successful fill synthesis. In this paper, we introduce compressed fill strategies which exploit the GDSII array reference record (AREF) construct. We apply greedy and linear programming based optimization techniques, and obtain practical compressed filling solutions.