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With the adoption of various combinations of resolution enhancement techniques (RET) for IC lithography, different process constraints are placed on the IC layout. The final layout used for mask production is dramatically different than the original designer's intent. To insure that EDA tools developed for applying RET techniques can have optimal performance, layout methodology must change to create a ture “target” layer that represents the actual design intent. Verification of the final layout is then expanded from LVS and DRC to also include lithography process simultion, which compares results to this desired “target” and governs the application of RET.