New approaches to optical proximity correction in photolithography
Microelectronic Engineering
A comparison of some dynamic load-balancing algorithms for a parallel adaptive flow solver
Parallel Computing - Special issue on graph partioning and parallel computing
Adoption of OPC and the impact on design and layout
Proceedings of the 38th annual Design Automation Conference
A novel parallel adaptive Monte Carlo method for nonlinear Poisson equation in semiconductor devices
Mathematics and Computers in Simulation - Special issue: 3rd IMACS seminar on Monte Carlo methods - MCM 2001
An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18µm ASIC
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
Fast optical and process proximity correction algorithms for integrated circuit manufacturing
A unified optimization framework for microelectronics industry
Proceedings of the 8th annual conference on Genetic and evolutionary computation
Electronic design automation using a unified optimization framework
Mathematics and Computers in Simulation
Simulation-based evolutionary method in antenna design optimization
Mathematical and Computer Modelling: An International Journal
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A novel parallel optical proximity correction (OPC) technique is proposed for process distortion compensation of layout mask in design and fabrication of very large scale integration (VLSI) circuits. Based on a genetic algorithm (GA), rule- and model-based correction methods, and domain decomposition algorithms, a parallel OPC system is successfully developed for the layout mask correction of VLSI circuits on a Linux-based PC cluster with the message passing interface (MPI) libraries. Tested on several layout patterns, the implemented pattern-based partition scheme shows good accuracy for the OPC-corrected layout mask of VLSI designs. Computational and parallel benchmarks, such as speedup and efficiency, are achieved and exhibit excellent performance of the developed system. Our approach provides an alternative in developing advanced computer aided design (CAD) tools and benefits design and fabrication of system-on-chip (SoC).