Subwavelength lithography and its potential impact on design and EDA
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Pattern-Based Domain Partition Approach to Parallel Optical Proximity Correction in VLSI Designs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 13 - Volume 14
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
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The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in the sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASIC's. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.