Optimal phase conflict removal for layout of dark field alternating phase shifting masks
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
Practical iterated fill synthesis for CMP uniformity
Proceedings of the 37th Annual Design Automation Conference
Monte-Carlo algorithms for layout density control
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 2001 international symposium on Physical design
Hierarchical dummy fill for process uniformity
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reticle enhancement technology: implications and challenges for physical design
Proceedings of the 38th annual Design Automation Conference
Closing the smoothness and uniformity gap in area fill synthesis
Proceedings of the 2002 international symposium on Physical design
Information Processing Letters
Area Fill Generation With Inherent Data Volume Reduction
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CAD for nanometer silicon design challenges and success
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
Is your layout density verification exact?: a fast exact algorithm for density calculation
Proceedings of the 2007 international symposium on Physical design
Fill for shallow trench isolation CMP
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Integrative 3D modelling of complex carving surface
Computer-Aided Design
Microelectronic Engineering
Provably good and practically efficient algorithms for CMP dummy fill
Proceedings of the 46th Annual Design Automation Conference
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient method for gradient-aware dummy fill synthesis
Integration, the VLSI Journal
Hi-index | 0.03 |
In very deep-submicron very large scale integration (VLSI), manufacturing steps involving chemical-mechanical polishing (CMP) have varying effects on device and interconnect features, depending on local characteristics of the layout. To reduce manufacturing variation due to CMP and to improve performance predictability and yield, the layout must be made uniform with respect to certain density criteria, by inserting “fill” geometries into the layout. To date, only foundries and special mask data processing tools perform layout post-processing for density control. In the future, better convergence of performance verification flows will depend on such layout manipulations being embedded within the layout synthesis (place-and-route) flow. In this paper, we give the first realistic formulation of the filling problem that arises in layout optimization for manufacturability. Our formulation seeks to add features to a given process layer, such that (1) feature area densities satisfy prescribed upper and lower bounds in all windows of given size and (2) the maximum variation of such densities over all possible window positions in the layout is minimized. We present efficient algorithms for density analysis, notably a multilevel approach that affords user-tunable accuracy. We also develop exact solutions to the problem of fill synthesis, based on a linear programming approach. These include a linear programming (LP) formulation for the fixed-dissection regime (where density bounds are imposed on a predetermined set of windows in the layout) and an LP formulation that is automatically generated by our multilevel density analysis. We briefly review criteria for fill pattern synthesis, and the paper then concludes with computational results and directions for future research