Computational geometry: algorithms and applications
Computational geometry: algorithms and applications
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
Proceedings of the 37th Annual Design Automation Conference
Closing the smoothness and uniformity gap in area fill synthesis
Proceedings of the 2002 international symposium on Physical design
An enhanced multilevel routing system
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Performance-impact limited area fill synthesis
Proceedings of the 40th annual Design Automation Conference
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Multilevel full-chip routing for the X-based architecture
Proceedings of the 42nd annual Design Automation Conference
Unification of partitioning, placement and floorplanning
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A novel framework for multilevel full-chip gridless routing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Multilevel full-chip gridless routing considering optical proximity correction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A layout dependent full-chip copper electroplating topography model
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
BoxRouter: a new global router based on box expansion and progressive ILP
Proceedings of the 43rd annual Design Automation Conference
Novel full-chip gridless routing considering double-via insertion
Proceedings of the 43rd annual Design Automation Conference
Wire density driven global routing for CMP variation and timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Novel wire density driven full-chip routing for CMP variation control
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Filling algorithms and analyses for layout density control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical area computation via Voronoi diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DUNE-a multilayer gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pattern routing: use and theory for increasing predictability and avoiding coupling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MR: a new framework for multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MARS-a multilevel full-chip gridless routing system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk- and performance-driven multilevel full-chip routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel Full-Chip Routing With Testability and Yield Enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMP Fill Synthesis: A Survey of Recent Studies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routing for manufacturability and reliability
IEEE Circuits and Systems Magazine
Dummy fill optimization for enhanced manufacturability
Proceedings of the 19th international symposium on Physical design
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Stitch-aware routing for multiple e-beam lithography
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.03 |
As nanometer technology advances, the post chemical-mechanical polishing (CMP) topography variation control becomes crucial for manufacturing closure. To improve the CMP quality, dummy-feature filling is typically performed by foundries after the routing stage. However, filling dummy features may greatly degrade the interconnect performance and significantly increase the input data in the following time-consuming reticle enhancement techniques. It is, thus, desirable to consider wire-density uniformity during routing to minimize the side effects from aggressive post-layout dummy filling. In this paper, we present a new full-chip grid-based routing system considering wire density for reticle planarization enhancement. To fully consider a wire distribution, the router applies a novel two-pass top-down planarity-driven routing framework, which employs new density critical area analysis based on Voronoi diagrams and incorporates an intermediate stage of a density-driven layer/track assignment based on incremental Delaunay triangulation. Experimental results show that our methods can achieve a more balanced wire distribution than state-of-the-art works.