DTR: a defect-tolerant routing algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Post-route optimization for improved yield using a rubber-band wiring model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Prelayout interconnect yield prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Should Yield be a Design Objective?
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Convex Optimization
Timing driven track routing considering coupling capacitance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimizing yield in global routing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
An Optimal Solution for the Channel-Assignment Problem
IEEE Transactions on Computers
Critical area computation via Voronoi diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing- and crosstalk-driven area routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
Proceedings of the 45th annual Design Automation Conference
A novel wire-density-driven full-chip routing system for CMP variation control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detailed-routing algorithms for dense pin clusters in integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dead via minimization by simultaneous routing and redundant via insertion
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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In this paper, we propose TROY, the first track router with yield-driven wire planning to optimize yield loss due to random defects. As the probability of failure (POF) computed from critical area analysis and defect size distribution strongly depends on wire ordering, sizing, and spacing, track routing plays a key role in effective wire planning for yield optimization. TROY formulates wire ordering into a preference-aware minimum Hamiltonian path problem. For simultaneous wire sizing and spacing optimization, TROY solves it optimally by formulating the problems into a second order conic programming (SOCP). Experimental results show that TROY can reduce the random-defect yield loss by 18% on average without any overhead in wirelength, compared with the widely used greedy approach.