Enhanced network flow algorithm for yield optimization
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A net-oriented method for realistic fault analysis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Fast Multi-Layer Critical Area Computation
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Timing-driven cell layout de-compaction for yield optimization by critical area minimization
Proceedings of the conference on Design, automation and test in Europe: Proceedings
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Timing-aware cell layout de-compaction for yield optimization by critical area minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A yield-driven gridless router
Journal of Computer Science and Technology
Lithography-aware layout compaction
Proceedings of the great lakes symposium on VLSI
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