On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Design for manufacturability and yield
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
DTR: a defect-tolerant routing algorithm
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Large-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
Small-area fault clusters and fault tolerance in VLSI circuits
IBM Journal of Research and Development
A net-oriented method for realistic fault analysis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Post-route optimization for improved yield using a rubber-band wiring model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Layout compaction for yield optimization via critical area minimization
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Incorporating Yield Enhancement into the Floorplanning Process
IEEE Transactions on Computers
Fast Multi-Layer Critical Area Computation
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Efficient critical area estimation for arbitrary defect shapes
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Yield and Routing Objectives in Floorplanning
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Determination of Yield Bounds Prior to Routing
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Yield Estimation of VLSI Circuits with Downscaled Layouts
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Layer assignment for yield enhancement
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical critical area extraction with the EYE tool
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing Environment
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Yield model for fault clusters within integrated circuits
IBM Journal of Research and Development
Critical area computation via Voronoi diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Stochastic interconnect layout sensitivity model
Proceedings of the 2007 international workshop on System level interconnect prediction
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects
Journal of Electronic Testing: Theory and Applications
How to consider shorts and guarantee yield rate improvement for redundant wire insertion
Proceedings of the 2009 International Conference on Computer-Aided Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
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The advent of deep submicron technologies with larger die sizes lends itself to an increase in fabrication cost. An appropriate yield forecast renders significant benefits in both time-to-market and manufacturing cost prediction. Yield forecasting is essential for the development of new products as it effectively shows if a design is feasible of meeting its cost objectives or not. In mature manufacturing processes, spot defects are the main detractors in the successful outcome of an IC. Their manifestation is as local disturbances of silicon layer structures. Spot defects are in essence random phenomena occurring on the wafer with certain stochastic size, spatial distribution, and frequency of occurrence per unit area. To verify the robustness of an IC it is necessary to extract its “critical areas”. The so-called critical areas are the places in the layout where defects can induce and IC faulty behavior such as a short or a break circuit. A figure of merit that measures the layouts robustness is obtained as the ratio of the total critical area to the layout area. This figure of merit is known as defect sensitivity. Knowledge of the designs defect sensitivity and the stochastic behavior of defects in the manufacturing line is used to ultimately predict yield.This tutorial reviews the basics on spot defect modeling, critical area modeling and its application in interconnect yield analysis.